1. Field of the Invention
The present invention generally relates to the field of manufacturing and package of microelectronic devices, and, more particularly, to a method of forming molded standoff structures on integrated circuit devices.
2. Description of the Related Art
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry having a high density of very small components. In a typical process, a large number of die are manufactured on a single wafer using many different processes that may be repeated at various stages (e.g., implanting, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarizing, etching, etc.). Each of the die typically include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are the external electrical contacts on the die through which the supply voltage, signals, etc. are transmitted to and from the integrated circuitry. The die are then separated from one another (i.e., singulated) by backgrinding and cutting the wafer. After the wafer has been singulated, the individual die are typically “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines and ground lines.
An individual die can be packaged by electrically coupling the bond pads on the die to arrays of pins, ball pads or other types of electrical terminals, and then encapsulating the die to protect it from environmental factors (e.g., moisture, particulates, static electricity and physical impact). For example, in one application, the bond pads can be electrically connected to contacts on an interposer substrate that has an array of ball pads. The die and a portion of the interposer substrate are then encapsulated with molding compound.
Electronic products require packaged microelectronic devices to have an extremely high density of components in a very limited space. For example, the space available for memory devices, processors, displays and other microelectronic components is quite limited in cell phones, PDAs, portable computers and many other products. As such, there is a strong drive to reduce the height of the packaged microelectronic device and the surface area or “footprint” of the microelectronic device on a printed circuit board. Reducing the size of the microelectronic device is difficult because high performance microelectronic devices generally have more bond pads, which result in larger ball grid arrays and thus larger footprints.
Image sensor die present additional packaging problems. Image sensor die include an active area that is responsive to electromagnetic radiation, e.g., light emitted from a light source. In packaging, it is important to cover and protect the active area without obstructing or distorting the passage of light or other electromagnetic radiation. Typically, an image sensor die is packaged by placing the die in a recess of a ceramic substrate and attaching a glass window to the die over the active area to hermetically seal the package.
FIG. 1 is a schematic, partial cross-sectional view of an illustrative example of a prior art image sensor die 10 formed in a semiconducting substrate 12. The image sensor die 10 comprises a window or glass 14 that is positioned above an active area 18 formed in the substrate 12. The active area 18 typically contains a plurality of sensor cells (not shown) that are responsive to electromagnetic radiation that passes through the window 14. The image sensor die 10 further includes a plurality of bond pads 22 and a schematically depicted integrated circuitry 20 that is electrically coupled to the bond pads 22 and the active area 18. An adhesive or epoxy 16 is used to attach the window 14 to the substrate 12.
Also depicted in FIG. 1 are a plurality of standoff structures 24 that may be formed on the substrate 12. Among other things, the standoff structures 24 are provided to maintain at least a set distance (corresponding to the height of the standoff structures 24) between the glass 14. Such standoff structures 24 may not be present in all applications
One illustrative technique for manufacturing the standoff structures 24 involves the use of traditional equipment used in manufacturing integrated circuit devices. For example, a sheet of glass, typically supplied as a square or rectangular piece of material, is initially cut into so-called “glass rounds.” These glass rounds have substantially the same round configuration as that of the semiconducting substrates, e.g., eight to twelve inches in diameter, that are used in manufacturing integrated circuit devices. After the glass rounds are formed, the standoff structures 24 are formed using traditional processing tools commonly found in semiconductor manufacturing operations. For example, the glass rounds may be positioned in a photolithography tool and the standoff structures 24 may be formed by performing traditional photolithography processes, e.g., spin-coat, soft-bake, expose, develop, hard-bake. Of course, using this technique, the standoff structures 24 may have any desired shape or configuration. Another technique might involve deposition of a layer of material on the glass round, followed by the formation of a masking layer, e.g., a patterned layer of photoresist material. Third, a traditional etching process may be performed to define the standoff structures 24 from the layer of material.
After the standoff structures 24 are formed, the glass round is then cut into a plurality of individual glass pieces or windows 14 that will be positioned over individual die, as depicted in FIG. 1. The aforementioned process of forming the standoff structures 24 is relatively expensive and time-consuming. Moreover, employing such manufacturing techniques may occupy very valuable semiconductor manufacturing equipment and therefore prevent the use of such equipment for manufacturing integrated circuit die.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.